Kugwiritsa Ntchito Ma Differential Oscillator mu High-Speed ​​FPGAs

Kugwiritsa Ntchito Ma Differential Oscillator mu High-Speed ​​FPGAs

Ma oscillator osiyanasiyana ali ndi ntchito zofunika kwambiri pakupanga-kuthamanga kwambiri kwa FPGA, makamaka m'makina omwe ali ndi zofunika kwambiri kuti azitha kulondola mawotchi, -kutha kusokoneza, ndi kukhulupirika kwa ma siginecha, monga:

Mawonekedwe apamwamba-othamanga kwambiri (PCIe, SFP+/QSFP, 10G Ethernet, DDR4/DDR5)

Zambiri-zopeza ma data pamakina

Njira zoyankhulirana mwachangu-(SerDes)

Njira zolumikizira zolondola (kudumpha nthawi, kuyendetsa kwa ADC/DAC)

Kodi Differential Oscillator ndi chiyani?

Differential Oscillator ndi crystal oscillator yogwira ntchito yomwe imatulutsa zizindikiro zosiyana (monga LVDS, LVPECL, HCSL), kupanga mawotchi awiri (CLK + ndi CLK-) omwe amatembenuzidwa wina ndi mzake. Zimasiyana ndi ma oscillator achikhalidwe amodzi ({2}}monga CMOS-zotulutsa zotulutsa).

Ubwino wa Zizindikiro Zosiyanasiyana:

Kugwiritsa Ntchito Ma Differential Oscillator mu High-Speed ​​FPGAs

Ikugwira ntchito ngati Wotchi Yolozera kwa High-Mawonekedwe Othamanga

Mawotchi othamanga kwambiri-monga PCIe, 10G/25G Ethernet, ndi SATA akuyenera kugwiritsa ntchito mawotchi osiyanasiyana;

100 MHz kapena 156.25 MHz osiyana oscillators (mwachitsanzo, HCSL/LVDS linanena bungwe) amagwiritsidwa ntchito;

Ma modules othamanga-othamanga kwambiri (Ma Transceivers) monga GTX/GTH/GTP mkati mwa FPGA amafunikira mawotchi olozera mosiyanasiyana.

✅ Mgwirizano Wodziwika:

Differential Oscillator → FPGA GTREFCLK0/1 (mapini apamwamba-atali kwambiri)

Core Clock Gwero la Mtengo wa Clock

M'makina-okwera kwambiri-makina othamanga, chotengera chosiyana chimayendetsa chip chogawa mawotchi (monga SI5341/AD9528), chomwe kenaka chimatulutsa mawotchi ambiri;

Ndiwoyenera kuyanjanitsa koloko muzolumikizana zambiri za ADC, DAC, ndi FPGA.

✅ Chithunzi chojambula:

Differential Oscillator → Clock Management Chip (mwachitsanzo, PLL / Fanout Buffer)

↓

Mawotchi Angapo → FPGA/ADC/DAC

Kuyendetsa FPGA Internal PLL/MMCM

Ma oscillator osiyanasiyana atha kupereka-mawotchi apamwamba kwambiri (monga kulowa mu FPGA kudzera mu mawonekedwe a IBUFDS), ndipo PLL/MMCM yamkati kenaka imatulutsa mawotchi pagawo lililonse ladongosolo; izi zimathandizira kuti wotchiyo ikhale yabwino komanso imachepetsa jitter ya wotchi yonse.

Mitundu Yosiyanasiyana Yosiyanasiyana ndi Kugwirizana kwa FPGA

✔ Ndikofunikira kugwiritsa ntchito mtundu wofananira wotulutsa monga momwe wopanga wa FPGA adapangira.

Malangizo a Differential Oscillator Selection

Ikani patsogolo ma protocol-mafuriji ovomerezeka:

PCIe: 100 MHz;

SFP +/10G Efaneti: 156.25 MHz;

25G / 40G Efaneti: 312.5 MHz;

JESD204B/C: 250 MHz, 312.5 MHz, 625 MHz, etc.

Onani mndandanda wa mawotchi ovomerezeka muzolemba zovomerezeka za FPGA;

Low jitter ndizovuta kwambiri:

RMS jitter < 0.5 ps (yofunika pa malo apamwamba-pamalo othamanga);

Chofunika kwambiri kwa PCIe, JESD204C, ndi 10G/25G Ethernet.

✅ Mafupipafupi Osiyanasiyana a Oscillator mu High-Speed ​​FPGAs

✔ Pamitundu ina, tikulimbikitsidwa kuti mulumikizane ndi ogulitsa ku Hangjing kapena mainjiniya aukadaulo kuti mupeze malingaliro ofananira amtundu wamtundu.

Chidule

Ma oscillator osiyanasiyana ali pafupifupi gawo lokhazikika m'makina amakono apamwamba-a FPGA ndipo ndi zida zazikulu zomwe zimatsimikizira-kulankhulana kwachangu ndi kuyanjanitsa kwadongosolo.

Ngati muli ndi mtundu wina wa FPGA (monga Xilinx Zynq Ultrascale+, Intel Stratix 10), mtundu wosiyana wa oscillator, kapena mawonekedwe olumikizirana (monga PCIe Gen3/SFP+), Suzhou Hangjing atha kukuthandizani kupangira chiwembu choyenera kwambiri chosinthira wotchi ndi kapangidwe kake kolumikizana.